USB 3.0设备中并行循环冗余校验的研究与实现
Research and implementation of the parallel CRC in USB 3.0 device
-
摘要: 针对串行循环冗余校验(CRC)算法不适于高速传输且不易于硬件实现的问题,结合USB 3.0设备中CRC的特点,推导出一种并行CRC算法,并用Verilog硬件编程语言加以实现.仿真试验表明,并行CRC校验算法具有更高的数据吞吐率,能降低时钟频率,易于硬件实现.Abstract: Aiming at the problem that the serial CRC check algorithm is not suitable for high-speed transmission and not easy to hardware realization,a parallel CRC algorithm was deduced base on the characteristics of the CRC in the USB device,and was implemented with Verilog hardware programming language.The simulation results showed that parallel CRC algorithm has a higher data throughput rate and can reduce the clock frequency.It's easier to implement in hardware.
-
Key words:
- USB 3.0 device /
- cyclic redundancy check (CRC) /
- parallel algorithm
-
-
[1]
于工.信息与编码简明教程[M].北京:国防工业出版社,2007:67-80.
-
[2]
蒋安平.循环冗余校验码(CRC)的硬件并行实现[J].微电子学与计算机,2007,24(2):107.
-
[3]
常天海,胡鉴.基于FPGA的CRC并行算法研究与实现[J].微处理机,2010(2):45.
-
[4]
程超,程善美.Unfolding算法实现的高速并行CRC电路的VLSI设计[J].微电子学与计算机,2002(12):68.
-
[5]
Shukla S,Bergman N W.Signle bit error correction implementation in CRC-16 on FPGA[C]//Field Programmable Technology,Piscataway:The Institute of Electrical and Electronics Engineers,2004.
-
[1]
计量
- PDF下载量: 12
- 文章访问数: 784
- 引证文献数: 0